Design of low cost ROM based test generators
作者： G. Edirisooriya , J.P. Robinson
DOI: 10.1109/VTEST.1992.232725
关键词:
摘要: A data compression technique for ROM based built-in test generators of combinational circuits is described. Some the pattern bits are computed using reduced stored in combined with address accessing ROM. experimental results presented ISCAS benchmark and random data. >
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