Transformed pseudo-random patterns for BIST

摘要: This paper presents a new approach for on-chip test pattern generation. The set of patterns generated by pseudo-random generator (e.g., an LFSR) is transformed into that provides the desired fault coverage. transformation performed small amount mapping logic decodes sets don't detect any faults and maps them hard-to-detect faults. purely combinational placed between circuit under (CUT). A procedure designing so it satisfies length coverage requirements described. Results are shown benchmark circuits which indicate LFSR plus reduces required particular orders magnitude compared with using alone. These results previously published other methods, proposed method requires much less overhead to achieve same length.