Continuous self-verify of configuration memory in programmable logic devices
作者： Jeffrey Byrne , Mark Moyer
DOI:
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摘要: A programmable logic device (5) such as an FPGA or CPLD is configured to verify the integrity of its configuration data (40) during operation device. The includes a checksum calculation engine (50) calculate based upon (40). comparator (60) compares calculated previously-calculated data.
lens.org 参考文章(15)
Ramesh C. Varshney, Test system for segmented memory ,(1980)
Kapil Shankar, Om P. Agrawal, Arthur H. Khu, Integrated circuit programmable sequencing element apparatus ,(1993)
Kevin A. Norman, Programmable integrated circuit micro-sequencer device ,(1987)
John Robert McDonald, John Lowell Zeller, Thomas Scott Gee, Nonvolatile memory implementation for electronic devices ,(1999)
Austin H. Lesea, Integrated testing of serializer/deserializer in fpga ,(2002)
Tord Lennart Haulin, A fault tolerant queue system ,(1994)
Rakesh H. Patel, Michael Hsiao-Ming Chu, Programming programmable transistor devices using state machines ,(1995)
William A. Gibson, Richard L. Bishop, Data processing system and information scanout employing checksums for error detection ,(1977)
Thomas A. Kean, Programmable switch for FPGA input/output signals ,(2000)
Gregory G. Finn, Steven M. Hotz, Craig M. Rogers, Method and network interface logic for providing embedded checksums ,(1996)