作者: Kazuyuki Tanaka
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摘要: A display processor for a raster-display type system comprising memory with the capacity of storing at least one page video information to be displayed over screen cathode-ray tube and (CRT) control circuit which divides frequency externally applied clock pulse generate address signal vertical horizontal sync signals, being while signals are CRT device. The present invention further adds comparator compares external synchronizing internal responds output from permit or inhibit passage circuit. plurality such processors used can synchronized in operation so that pages mutually superimposed relationship on same face tube, whereby versatile displays presented.