Power down mode for computer system

摘要: A computer system includes a CPU and VGA/LCD controller interacting with main memory for processing input data displaying it on an LCD panel screen that plurality of row column drive chips the panel. Each chip driver control logic. frame rate modulated grey-scale signal is fed from processor to memory. Timing signals, including horizontal vertical clocks, shift are circuit which read out display screen. Upon detection absence update information two full periods, enters power down mode by re-mapping black-and-white data, stopping clock, disabling portions its sequencer so latter off mode. Stopping clock causes enter self-refresh in stored repetitively under signals.