Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor

摘要: Speculative pre-fetching and pre-flushing of additional cache lines minimize miss latency coherency check an out order instruction execution processor. A pre-fetch/pre-flush slot (DPRESLOT) is provided in a memory queue (MQUEUE) the out-of-order The DPRESLOT monitors transactions between system interface, e.g., bus, address reorder buffer (ARBSLOT) and/or interface (CCCSLOT). When detected, causes one or more addition to data line, which caused current miss, be pre-fetched from hierarchy into (DCACHE) anticipation that would required near future. write back detected as result check, lines, line currently being written back, pre-flushed respective processor owns by requesting logic included prevents request for when another has already been made data.