Mechanism for implementing cache line fills
作者： Sailesh Kottapalli
DOI:
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摘要: The present invention provides a mechanism for implementing cache line fills. In response to target address, decoder generates primary and secondary look-ups first on standard pseudo ports, respectively. Responsive miss by the access, data block is returned cache, having size determined hit/miss signal generated look-up.
lens.org 参考文章(12)
Thomas E. Westberg, Intelligent cache memory and prefetch method based on CPU data fetching characteristics ,(1992)
Joel S. Emer, Simon Steely, Edward J. McLellan, Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted ,(1997)
David B. Witt, Computer memory architecture including a replacement cache ,(1993)
David J. Harriman, Zohar Bogin, Zdzislaw A. Wirkus, Satish Acharya, Method and system for servicing cache line in response to partial cache line request ,(2000)
James R. Anderson, Ernest T. Lampe, Jeff J. Baxter, Method and apparatus for filtering prefetches to provide high prefetch accuracy using less hardware ,(2000)
Jay C. Pattin, Earl T. Cohen, Slave cache having sub-line valid bits updated by a master cache ,(1996)
David Jerome Johnson, Gregg B Lesartre, Speculative pre-fetching additional line on cache miss if no request pending in out-of-order processor ,(2000)
Glenn David Gilda, Steven Lee Gregor, Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system ,(2000)
Juay K. Tan, Robert W. Kwong, I/O cache with dual tag arrays ,(1993)