作者: Hema Mehta , Harsupreet Kaur
关键词:
摘要: This paper focuses on studying the impact of parasitic capacitance ( ${C}_{p}$ ) performance nanoscale graded channel (GC) negative (NC) silicon-on-insulator (SOI) FET at elevated temperatures. The device has been extensively explored for a range values temperature 300–400 K by employing simulation framework that uses TCAD models with Landau Khalatnikov equation. advantages GC design and NC phenomenon have investigated wide optimum obtained to achieve substantial enhancement in key parameters such as differential voltage amplification, subthreshold swing (below 60 mV/dec), transconductance, transconductance efficiency, output characteristics, unity gain frequency.