Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor

摘要: An approach to accelerating fault simulation using a vector super computer is described and the zero-delay, two-valued of gate-level combinational circuits discussed. As processor oriented technique, an algorithm was developed that based on parallel technique. In can be accelerated (given enough lengths obtained) maximum 20 times faster operations currently available by extending processing unit from one word multiple words. However, when generate or evaluate test patterns performed, length not obtained computation time increases if large attempted because detected faults are dropped. order address problems, dynamic, two-dimensional, technique proposed. this utilizing both pattern parallelism, dropping efficiently used adjusting two parallelism factors complementarily pass pass. The further reduced combining with selective tracing under notion propagation. experiments FACOM show speed 10 about 15 through vectorization. >