Dynamic combined pattern-parallel and fault-parallel fault simulation on computational RAM
作者： A.L.-C. Kwong , B.F. Cockburn , D.G. Elliott
DOI: 10.1109/CCECE.1999.807238
关键词:
摘要: Computational RAM (C/spl middot/RAM) is a logic-enhanced memory architecture that supports massively-parallel bit-serial computation. Previous work (J.A. Waicukauski et al., 1987; B.F. Cockburn 1998, A.L.-C. Kwong, 1998) investigated the implementation of fault-parallel and pattern-parallel fault simulation algorithms on C/spl middot/RAM. The strategy was found to be efficient at start but inefficient end. converse behaviour observed for strategy. A dynamic hybrid algorithm combines strategies in an adjustable proportion so as obtain best aspects both. This paper describes simulator middot/RAM models detection combinational logic stuck-at faults, transition faults order 1, CMOS transistor stuck-open faults.
sci-hub.se 参考文章(7)
B.F. Cockburn, A.L.-C. Kwong, D.G. Elliott, Parallel implementations of transition fault simulation on computational RAM (C/spl middot/RAM) canadian conference on electrical and computer engineering. ,vol. 1, pp. 5- 8 ,(1998) , 10.1109/CCECE.1998.682536
T.M. Niermann, Wu-Tung Cheng, J.H. Patel, PROOFS: a fast, memory-efficient sequential circuit fault simulator IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 11, pp. 198- 207 ,(1992) , 10.1109/43.124398
K.M. Thompson, Intel and the myths of test IEEE Design & Test of Computers. ,vol. 13, pp. 79- 81 ,(1996) , 10.1109/54.485786
John Waicukauski, Eric Lindbloom, Barry Rosen, Vijay Iyengar, Transition Fault Simulation IEEE Design & Test of Computers. ,vol. 4, pp. 32- 38 ,(1987) , 10.1109/MDT.1987.295104
F. Brglez, A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN Proc. Intl. Symp. Circuits and Systems, 1985. ,(1985)
D.G. Elliott, M. Stumm, W.M. Snelgrove, C. Cojocaru, R. Mckenzie, Computational RAM: implementing processors in memory IEEE Design & Test of Computers. ,vol. 16, pp. 32- 41 ,(1999) , 10.1109/54.748803
N. Ishiura, M. Ito, S. Yajima, Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 9, pp. 868- 875 ,(1990) , 10.1109/43.57785