Shared synchronous memory with a switching circuit controlled by an arbiter and method for glitch free switching of a clock signal

摘要: A multiple agent system allowing each of a plurality agents, i.e., processors, to present different address, data, control and/or clock signals common shared synchronous memory. The from the agents is arbitrated in response memory access request determine winning agent. and are controlled so as prevent undesirable high frequency waveforms glitches being presented during an arbitration period including transition between previous owner's signal agent's signal. For instance, case signal, switching circuit disables for time at least about one phase arbiter before after period. In data signals, enable disactivation output