Synchronous dynamic memory device capable of operating over wide range of operation frequencies
作者： Kanji Oishi , Ken Shibata
DOI:
关键词: Signal 、 Synchronism 、 Electronic engineering 、 Clock domain crossing 、 Clock skew 、 Synchronous circuit 、 Digital clock manager 、 Phase-locked loop 、 Engineering 、 Asynchronous circuit
摘要: In a synchronous DRAM, internal clock signals in synchronism with fed from an external unit are generated by PLL circuit or DLL to eliminate signal delays. order provide dynamic RAM that is capable of stably operating over wide range frequencies; change-over provided which changes the variable frequencies delay time based upon mode-setting information unit.
google.de 参考文章(4)
Edmund A. Reese, Ngai H. Hong, Clock voltage generator for semiconductor memory ,(1978)
Hidenori Nomura, Tomio Nakano, Dynamic random access memory having improved refresh timing ,(1989)
Mitsugi Ogura, Naokazu Miyawaki, Memory clock pulse generating circuit with reduced peak current requirements ,(1983)