Asynchronously-accessible memory devices and access methods

作者: Jeffrey Mailloux , Kevin Ryan , Brett Williams , Todd Merritt

DOI:

关键词: Semiconductor memoryPhysical addressComputer hardwareRegistered memoryFlat memory modelEmbedded systemInterleaved memoryMemory addressMemory address registerComputer scienceAddress bus

摘要: Apparatus and methods may operate to switch between burst modes pipelined without using a WCBR (write column address select before row select) cycle, as well an external data path, instruct memory perform desired operation, the operation until terminated.

参考文章(114)
Neal D. Margulis, Takatoshi Ishii, Burst-mode DRAM ,(1993)
Anthony M. Olson, Thomas N. Robinson, Babu Rajaram, Main memory access in a microprocessor system with a cache memory ,(1987)
Raymond A. Ward, Scott A. Dresser, Flexible addressing for DRAMS ,(1992)
Paul A. Santeler, Gary W. Thome, Lee B. Hinkle, John A. Landry, David R. Wooten, Memory controller that dynamically predicts page misses ,(1995)
Loren L. McLaury, Pipelined SAM register serial output ,(1991)