Semiconductor memory device with changeable input/output data bit arrangement

摘要: A dynamic type semiconductor memory device includes a plurality of data input/output nodes, /CAS buffers for generating column address strobe signals corresponding to each said and an input node carrying out only input. switching signal generation circuit generates first second indicating control modes. Memory cells in number the nodes are selected simultaneously from cell array. In operation mode A, is effected using one input/ouput node. case B, writing/reading via according signal. C, carried individually signals. Modes B C can be realized DRAM. Particularly, controlling respective signals, unnecessary bits prevented reduce power consumption prevent erroneous parity bit writing.