Testing system for reliable access times in ROM semiconductor memories

作者: Robert D. Catiller

DOI:

关键词: Registered memorySemiconductor memoryFlat memory modelComputer hardwareComputer memoryElectronic engineeringComputer scienceMemory refreshSense amplifierAuxiliary memoryInterleaved memory

摘要: A testing circuit is disclosed for addressing and exercising a ROM-type memory splitting the same output data into two paths. One path used to temporarily hold time-interval after which it compared, in digital comparator, with on second path. When both paths compare equally, then known that no instability has occurred during time-interval. If miscompare occurs, comparator generates an error signal.

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Kohji Ishikawa, Kenji Kimura, Naoaki Narumi, Semiconductor memory test equipment ,(1980)
Robert E. Jones, Donald H. Wood, Memory address selector ,(1980)