Analog-digital converter with distributed sample-and-hold circuit

摘要: The disclosure relates to analog-digital converters. It is sought limit the power consumption and obtain a better compromise among different performance characteristics of computer. In general structure converter there are, firstly, coarse for most significant bits and, secondly, fine least bits. One them, generally, converter, has differential amplifiers [AD(1) AD(N)]receiving voltage be converted (Ve) reference voltage. proposed place sample-and-hold circuits [EB(1) EB(N)] at output these eliminate circuit that often placed upline with respect amplifiers.