作者: V.A. Shah , A. Dobbie , M. Myronov , D.R. Leadley
DOI: 10.1016/J.SSE.2011.03.005
关键词:
摘要: After a long period of developing integrated circuit technology through simple scaling silicon devices, the semiconductor industry is now embracing boosters such as strain for higher mobility channel material. Germanium logical supplement to enhance existing technologies, its material behaviour very close silicon, and create new functional devices that cannot be fabricated from alone (Hartmann et al. (2004) [1]). wafers are, however, both expensive less durable than their counterparts. Hence it highly desirable relaxed high quality Ge layer on Si substrate, with provision this does not unduly compromise planarity system. The two temperature method, proposed by Colace (1997) [2], can give smooth (RMS surface roughness below 1 nm) low threading dislocation density (TDD <10(8) cm(-2)) layers directly Si(0 0 1) wafer (Halbwax (2005) [3]), but these are currently order 1-2 mu m thick (2009) [4]). We present an in depth study layers, grown reduced pressure chemical vapour deposition (RP-CVD), effort reduce thickness. We report effect changing thickness, (LT) (HT) emphasising variation TDD, morphology relaxation. Within study, LT deposited substrate at 400 degrees C. This known generate monolayer islands (Park (2006) [5]), sufficiently maintain crystallinity whilst keeping epitaxial possible suppressing further island growth proceeding Frank-van der Merwe mode. also generates vast number dislocations, 10(8)-10(9) cm(-2), enable next HT step relax maximum amount possible. varying thickness studied depositing fixed (100 670 find allows Ge-on-Ge adatom transport minimise energy layer. final technique annealing dislocations generated glide, increasing degree relaxation, annihilate. TDD 10(7) cost significantly roughened surface.