作者: Fang-Ting Chou , Zong-Yi Chen , Hsing-Chien Chu , Chung-Chih Hung
DOI: 10.1109/ISCAS.2015.7168810
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摘要: This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed reference currents. The technique allows significant area savings without impairing static accuracy. also presents method to generate dual currents, whose design is compact and consumes low power. active DAC 0.36mm2 approximately. chip was fabricated by standard 0.18μm CMOS technology, 38mW at 180MS/s update rate 1.8V supply voltage.