A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC
作者： Xu Wu , Pieter Palmers , Michiel S. J. Steyaert
DOI: 10.1109/JSSC.2008.2004527
关键词: Nyquist rate 、 Low-power electronics 、 Spurious-free dynamic range 、 Engineering 、 Integral nonlinearity 、 CMOS 、 Electronic engineering 、 Clock rate 、 Digital-to-analog converter 、 Sampling (signal processing) 、 Electrical engineering
摘要: This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It is based on current steering binary weighted architecture and achieves 10-bit static linearity without calibration. Due to the use of pseudo-segmented structure instead thermometer decoder, operating speed can be up 4.5 GS/s. The DAC occupies 0.4 mmtimes0.5 mm in standard 130 nm CMOS technology. A spurious-free dynamic range (SFDR) more than 36 dB has been measured over complete Nyquist interval at sampling frequencies 3 power consumption GHz clock frequency for near-Nyquist sinusoidal output signal equals 29 mW .
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