A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect
作者： Santanu Sarkar , Swapna Banerjee
关键词: Linearity 、 Current source 、 Spurious-free dynamic range 、 Transistor 、 Least significant bit 、 Electrical engineering 、 Differential nonlinearity 、 CMOS 、 Electronic engineering 、 Engineering 、 Integral nonlinearity
摘要: This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (DAC)with optimum sizing sources. The DAC has been designed in 0.18 a#x03BC;m CMOS n-well technology provided by National Semiconductor. 10-bit is as 5+5, where 5-LSB bits are implemented binary and 5-MSB unary architecture. matching unit sources plays an important role determining overall linearity DAC. Static can be improved using larger area source transistors, sacrificing dynamic performances. At high frequency spectral performance degrades due to increased parasitic. In this work with sizes achieve static well simulation, achieves maximum DNL 0.248 LSB INL 0.440 LSB. spurious free range (SFDR) 59.79 dB for 5.37 MHz signal mismatch environment at 500 MSPS sampling rate. shows Nyquist SFDR 57 rate mismatch. consumes only 17.85 mW power 1.8 V supply.
sci-hub.se 参考文章(14)
Anne van den Bosch, Michiel Steyaert, Willy Sansen, An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converters Analog Integrated Circuits and Signal Processing. ,vol. 29, pp. 173- 180 ,(2001) , 10.1023/A:1011261330190
Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio di Giandomenico, Luca Gori, A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13/spl mu/m CMOS international solid-state circuits conference. pp. 250- 600 ,(2007) , 10.1109/ISSCC.2007.373388
Chi-Hung Lin, K. Bult, A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/ IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 1948- 1958 ,(1998) , 10.1109/4.735535
Mahdi Khafaji, Christoph Scheytt, Udo Jorges, Corrado Carta, Daniel Micusik, Frank Ellinger, SFDR considerations for current steering high-speed digital to analog converters bipolar/bicmos circuits and technology meeting. pp. 1- 4 ,(2012) , 10.1109/BCTM.2012.6352646
Yuanliang Li, Zhiqun Li, A low-power 6-bit D/A converter design for WSN transceivers international conference on communication technology. pp. 307- 310 ,(2011) , 10.1109/ICCT.2011.6157885
J. Deveugele, M.S.J. Steyaert, A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC IEEE Journal of Solid-State Circuits. ,vol. 41, pp. 320- 329 ,(2006) , 10.1109/JSSC.2005.862342
Wei-Te Lin, Tai-Haur Kuo, A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection IEEE Journal of Solid-state Circuits. ,vol. 47, pp. 444- 453 ,(2012) , 10.1109/JSSC.2011.2168651
M.A.F. Borremans, M.S.J. Steyaert, W. Sansen, A. van den Bosch, A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter IEEE Journal of Solid-state Circuits. ,vol. 36, pp. 315- 324 ,(2001) , 10.1109/4.910469
Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund, A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme IEEE Transactions on Very Large Scale Integration Systems. ,vol. 23, pp. 44- 53 ,(2015) , 10.1109/TVLSI.2014.2298055
Xu Wu, Pieter Palmers, Michiel S. J. Steyaert, A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC asian solid state circuits conference. ,vol. 43, pp. 2396- 2403 ,(2007) , 10.1109/JSSC.2008.2004527