Integrated circuit connection arrangement for minimizing crosstalk
作者： Molin Stuart B , Jiang Raymond Xin , Tu Shanghui Larry , Tasbas Befruz , Stuber Michael A
DOI:
关键词:
摘要: A semiconductor package includes a leadframe, having perimeter leads and ground voltage lead, bottom die flip-chip mounted to the top die. The has first frontside active layer with electrical contacts electrically connected backside portion, buried oxide situated between portion. is circuit portion by connection through layer. of lead contact minimize crosstalk.
lens.org 参考文章(93)
Jonathan Noquil, Juan Alejandro Herbsommer, Brian Ashley Carpenter, Osvaldo Jorge Lopez, Marie Denison, Integrating multi-output power converters having vertically stacked semiconductor chips ,(2015)
Yau-Wai Wong, Nan-Jang Chen, Sgs or gsgsg pattern for signal transmitting channel, and pcb assembly, chip package using such sgs or gsgsg pattern ,(2013)
Sinan Goktepeli, George P. Imthurn, Stuart B. Molin, Semiconductor-on-Insulator Integrated Circuit with Back Side Gate ,(2014)
Andrew N. Sawle, Eung San Cho, Chuan Cheah, Stacked Half-Bridge Package ,(2014)
Edward J. Rice, Method of fabrication lateral FET structure having a substrate to source contact ,(1986)
Jacek Korec, Osvaldo J. Lopez, Shuming Xu, Mosfet with gate pull-down ,(2010)
Andrew N. Sawle, Eung San Cho, Chuan Cheah, Stacked half-bridge package with a common leadframe ,(2013)
Sen Mao, Kyle Terrill, Frank Kuo, Method for fabricating stack die package ,(2013)
Jun Zhai, Stacked wafer ddr package ,(2013)
Jacek Korec, Wayne B. Grabowski, Richard K. Williams, Shekar S. Malikarjunaswamy, Trench-gated Schottky diode with integral clamping diode ,(1997)