作者: K. Itonaga , K. Mizuta , T. Kataoka , M. Yanagita , H. Ikeda
DOI: 10.1109/IEDM.2011.6131511
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摘要: We have developed a flat device structure, which we call “FLAT”, with no isolation grooves/ridges and Si substrate etching in the imaging area of CMOS Image Sensor (CIS). employed this FLAT structure to achieve 1.12 µm pitch pixel CIS 1.25 transistor/pixel architecture excellent image quality. It uses transistors(Trs) that generate greatly-reduced 1/f noise, isolators (Isos) increase saturation capacity (Qs) due increasing both effective photodiode (PD) PD potential under low dark current.