Combinational logic circuit optimization

摘要: Examples herein describe techniques for optimizing a hardware design an integrated circuit. Instead of trying multiple optimization strategies each time code is synthesized, the embodiments identifying optimal or best strategy particular combinational module in only one time. Then, synthesized future, synthesis tool recognizes and selects strategy. To do so, generates signature using circuit structure represented by netlist. The traverses netlist assigns unique integers to primary inputs, combination instances, outputs. These can then be fed into generator which outputs module.