Design for Reliability of Wafer Level MEMS packaging

摘要: The world has seen an unrivaled spread of semiconductor technology into virtually any part society. main enablers this rush are the decreasing feature size and constantly costs semiconductors. semiconductors in general caused by smaller size, higher yield larger production volumes. This made products containing cheaper thus reaching a market. enables more computing power same volume creating new markets growing application areas. increasing number appliances using components is also driving fast growth trend miniaturization electronic demands integration non-electrical functions to allow for large decreases weight possibly cost. Soon after first were developed Micro Electrical Mechanical Systems (MEMS) created. In 1960’s 1970’s experiments with MEMS done lab environments. can be used miniaturize enabling further system shrinkage increased function density. technologies, numerical simulations thesis provide designers design guideline creation process Wafer Level Thin Film Package (WLTFP) as well overview most likely failure modes high risk processes assembly. WLTFP’s miniature batch-process wafer scale encapsulation method that need space move or hold certain amount gas. chapters important processing steps subsequent assembly needed form plastic encapsulated package presented. Most common included: thinning, chip singulation, die-attach, wire bonding, overmoulding saw, trim, mark & form. thinning necessary thin such thickness it will fit desired package. Chip singulation dicing commonly diamond blade saw makes separates individual chips. Die-attach placement onto carrier, example lead frame, means glue. After dieattach connection IO carrier wirebonding. wire-bonding overflowed epoxy moulding compound protect inside from environment. finishing marking one complete product. product team faced multi-scale, multi-physics multi-timescale challenge. Nanometer dimensions impact millimeter hours operation change performs microsecond measurements. To address challenge integrated covers all intermediate processes. An influences on calculated shown chapter three. four properties layers investigated. investigation copper film deposited freestanding micro cantilevers. samples analyzed white light interferometry obtain initial geometry cantilever warpage. Using electrostatic pull-in pull down substrate voltage obtained. stiffness two layer derived voltage. Copper thicknesses 10 50 nanometer measured size-dependant proven. During WLTFP several found. tape active side easily break many WLTFP’s. happen during removal tape. foil potential leaves exposed water jet machine. Wire-bonding hazardous sensitive resonance, relatively easy mitigated calculation eigenmodes eigenfrequencies. associated pressure membranes due static cavity. five toolbox check weak spots investigate changes virtual prototyping instead physical prototyping. include simulation. use cohesive zones allows detailed loads WLTFP. six interface investigated peeling experiment combined simulations. characterization yields serve input aforementioned Design Experiments presented seven investigates influence major choices likelihood survival span WLTFP, corner rounding radius, cap presence pillar 18720 evaluated guidelines was derived. combination provides community tools chip-design stage. aids approach designing reduces time market iterations needed.