DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts
作者： Sachie Kuroda , Takashi Yamasaki
DOI:
关键词:
摘要: A DMA controller interrupts data transfer as needed to the bus use permit CPU and resumes when completes memory in burst mode which predetermined number of words is transferred between I/O device memory.
google.com.au 参考文章(6)
Mario Anthony Marsico, Ronald Julius Cooper, John Carmine Pescatore, Gilbert Stevens Burrus, Michael Raymond Marr, Paul Douglas Sullivan, Multiple port communications adapter apparatus ,(1986)
Surendar S. Magar, James F. Potts, Jerald G. Leach, L. Ray Simar, Data processing device with improved direct memory access ,(1991)
Mario Anthony Marsico, Ronald Julius Cooper, John Carmine Pescatore, Paul Douglas Sullivan, Multiplexed interrupt/dma request arbitration apparatus and method ,(1985)
Mario Anthony Marsico, John Carmine Pescatore, Michael Raymond Marr, Ronald Julius Cooper, Gilbert Steven Burrus, Multiple port integrated DMA and interrupt controller and arbitrator ,(1986)
Raphael Gollub, Multiplexed digital packet telephone system ,(1986)