Apparatus for transfer-controlling data by direct memory access
作者： Seido Hatae , Kazuyuki Mitsuishi
DOI:
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摘要: A bus controller provided with a buffer memory performs DMA data transfer between main storage unit of system and an input/output control local bus. An interruption section the keeps signal at response suppress upon detection end from on side, thus sending thereof to processor When is determined monitor in suppressed state, state released notice given processor. Even earlier bus, therefore, consistency sent ensured.
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