Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits

摘要: A method for making metal interconnections and buried plug structures multilevel on semiconductor integrated circuits was achieved. The utilizes a single patterned photoresist layer etching trenches in an insulating layer, while at the same time protecting device contact areas openings from being etched, thereby reducing process complexity manufacturing cost. After are formed, is removed by plasma ashing, deposited etched back or chem/mech polished to form concurrently contacts. surface of coplanar with surface, allowing be repeated several times complete necessary wiring needed wire-up maintaining planar surface.