A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing
作者： Craig R. Schlottmann , Samuel Shapero , Stephen Nease , Paul Hasler
DOI: 10.1109/JSSC.2012.2194847
关键词:
摘要: We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm2 350 nm-CMOS reconfigurable IC incorporates digital enhancements to increase compatibility in embedded systems. The chip contains 78 computational blocks (CABs) which house variety of processing elements. There are 36 general CABs with hundreds common primitives computation, 18 digital-to-analog converter (DAC) CABs, each 8-b compilable DAC capabilities, and 24 vector-matrix multiplier parallel processing. A floating-gate routing matrix connects these elements one another, both within individual between CABs. To facilitate interfacing dynamic reconfigurability, we included novel network volatile switches based on shift select registers that control switches. These dynamically controlled span all the rows columns internal routing, allowing run-time system modification scanning I/O. can also double as on-chip memory. introduce new hybrid switch matrix, includes eliminate previously observed mismatch issues provide highly precise highlight potential this digitally enhanced processor, demonstrate image transformer, an arbitrary waveform generator, FIR filter.
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