A mixed-signal approach to high-performance low-power linear filters

摘要: We present a new approach to the design of high-performance low-power linear filters. use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast arithmetic. To demonstrate effectiveness our approach, we have built 16-tap 7-b 200-MHz finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The uses pFETs store tap coefficients, electron tunneling hot-electron injection modify coefficient values, digital registers delay line, multiplying digital-to-analog converters multiply delay-line values with coefficients. measured maximum clock speed is 225 MHz; tap-multiplier resolution 7 b 200 MHz. total die area 0.13 mm/sup 2/. can readily scale longer lines.