Semiconductor memory configuration with a built-in-self-test
作者： Peter Pöchmüller
DOI:
关键词:
摘要: A semiconductor memory configuration, in particular a DRAM, which redundant cells, bit lines and word are determined for failed by built-in-self-test computing unit special algorithm.
lens.org 参考文章(3)
Grady Lawrence Giles, Kerry Ken Kanbe, William Clayton Bruce, Method and apparatus for testing an integrated memory device ,(1998)
V Swamy Irrinki, Thomas R Wik, Memory testing method for customer final check ,(1998)
Adam Kablanian, Saravana Soundararajan, Chuong T. Le, Thomas P. Anderson, Owen S. Bair, Method for repairing an ASIC memory with redundancy row and input/output lines ,(1998)