Method and apparatus for a dual substrate package
作者： Christopher L. Rumer , Kuljeet Singh
DOI:
关键词:
摘要: A semiconductor die having a through via formed therein is disclosed. first conductive layer on the front side of and second backside die, coupled with via. package substrate electrically layer, layer. In another embodiment, ball couples substrates. further flip chip bump attached to substrate.
lens.org 参考文章(15)
Takashi Iwamoto, Makoto Yoshimura, Dutta Amit, Takaharu Fujii, 3D-Semiconductor Package ,(2002)
John Marciniec, Kenneth R. Erikson, Timothy E. White, Acoustical array with multilayer substrate integrated circuits ,(2002)
Warren M. Farnworth, Surface mount IC using silicon vias in an area array format or same size as die array ,(1996)
Eugene H. Cloud, Leonard Forbes, Kie Y. Ahn, Structure and method for a high performance electronic packaging assembly ,(1998)
Thomas George Ference, Edmund Juris Sprogis, Claude Louis Bertin, Wayne John Howell, Highly integrated chip-on-chip packaging ,(1998)
Richard W. Gurtler, Syd R. Wilson, Jeffrey Pearse, Method of forming vias through two-sided substrate ,(1994)
Min-Chih John Hsuan, Integrated circuit with improved interconnect structure and process for making same ,(2002)
Donald A. Burkhart, Michael M. Chau, Materials for semiconductor device assemblies ,(1995)
Christopher Lee Tessler, Joseph Michael Sullivan, Ajay Prabhakar Giri, Multichip module having chips on two sides ,(2002)
Kazuaki Karasawa, Takeshi Shioga, Kazuaki Kurihara, Capacitor and semiconductor device and method for fabricating the semiconductor device ,(2003)