Current-mode algorithmic pipeline analog-to-digital converter
作者： A.J. Correia , J.C. Guilherme , J.E. Franca
DOI: 10.1109/APCAS.1996.569300
关键词:
摘要: Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing compact algorithmic processing circuitry in each stage. The prototype chip fabricated 1.2 /spl mu/m occupies 0.655 mm/sup 2/ silicon area and dissipates 50 mW at 5 V supply.
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