iterative test generation and diagnostic method based on modeled and unmodeled faults

摘要: A diagnostic and characterization tool applicable to structural VLSI designs address problems associated with fault tester interactive pattern generation ways of effectively reducing test time while achieving greater fail resolution. Empirical data drives the creation adaptive patterns which localize a precise location. This process iterates until necessary localization is achieved. Both signatures callouts as well are stored in library speed The parallel application provide an efficient use resources overall time.