Modeling and analysis of leakage power considering within-die process variations
作者： Ashish Srivastava , Robert Bai , David Blaauw , Dennis Sylvester
关键词:
摘要: We describe the impact of process variation on leakage power for a 0.18 /spl mu/m CMOS technology. show that variability, manifested in gate length (L/sub drawn/), oxide thickness (T/sub ox/), and channel dose (N/sub sub/), can drastically affect current. first present Monte Carlo-based simulation results current various gates when parameters are varied both individually concurrently. then derive an analytical model to estimate mean standard deviation as function parameter distributions. demonstrate match well with Monte-Carlo simulations also statistical is significantly different from predicted using nominal case file.
core.ac.uk
acm.org
sci-hub.se 参考文章(8)
Athanasios Papoulis, Probability, random variables and stochastic processes ,(1965)
Siva Narendra, Dimitri Antoniadis, Vivek De, Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation international symposium on low power electronics and design. pp. 229- 232 ,(1999) , 10.1145/313817.313932
Bruno O. Shubert, Harold J. Larson, Random variables and stochastic processes Wiley. ,(1979)
P. M. Zeitzoff, A. F. Tasch, W. E. Moore, S. A. Khan, D. Angelo, Modeling of manufacturing sensitivity and of statistically based process control requirements for a 0.18 μm NMOS device Characterization and Metrology for ULSI Technology. ,vol. 449, pp. 73- 81 ,(1998) , 10.1063/1.56859
Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks international symposium on low power electronics and design. pp. 239- 244 ,(1998) , 10.1145/280756.280917
Chenming Hu, Device and Technology Impact on Low Power Electronics Springer, Boston, MA. pp. 21- 35 ,(1996) , 10.1007/978-1-4615-2307-9_2
R.X. Gu, M.I. Elmasry, Power dissipation analysis and optimization of deep submicron CMOS digital circuits IEEE Journal of Solid-state Circuits. ,vol. 31, pp. 707- 713 ,(1996) , 10.1109/4.509853
S. Tyagi, M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, M. Hussein, P. Jacob, C. Kenyon, C. Lo, B. McIntyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, M. Bohr, A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects international electron devices meeting. pp. 567- 570 ,(2000) , 10.1109/IEDM.2000.904383