LDPC erasure decoding for flash memories

摘要: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC having a BER less than predetermined value, the SSD 1-bit read (single read) hard-decision decoder access memory. If detects an uncorrectable error, then 1.5-bit (two reads) erasure-decision raw between two other values, omits use of and only Variations similarly MLC Some controllers dynamically switch erasure-based decoders based on dynamic selection criteria.