作者: Yukio Chiba , Katsumi Otsuka , Susumu Igarashi , Tetsuya Tateno , Makoto Satoh
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摘要: This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means. For this purpose, in order to determine length length, two different decode processes are executed, overall is separated into three stages, i.e., stage for shifting out word of data, stage, symbol determination & these stages executed manner.