Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
作者： Chadha Sundeep , Bishop James W , Nguyen Dung Q , Barrick Brian D , Terry David R
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摘要: Operation of a multi-slice processor that includes execution slices and dispatch network the implementing hardware level transfer an thread between slices. such responsive to switch signal: halting one or more instructions retrieved from instruction cache; generating plurality first slice second slice; dispatching instead transferring, in dependence upon switching generator, slice.
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