Asymmetric multi-core processor with native switching mechanism

摘要: A processor includes first and second processing cores configured to support respective subsets of features its instruction set architecture (ISA) feature set. The subset is less than all the ISA are different but their union core detects a thread, while being executed by rather core, attempted employ not in and, response, indicate switch from execute thread. unsupported may be an or operating mode. also made if lower performance/power over-utilized higher under-utilized.