Verifiable ASICs

摘要: A manufacturer of custom hardware (ASICs) can undermine the intended execution that hardware, high-assurance thus requires controlling manufacturing chain. However, a trusted platform might be orders magnitude worse in performance or price than an advanced, untrusted platform. This paper initiates exploration alternative: using verifiable computation (VC), ASIC computes proofs correct execution, which are verified by processor ASIC. In contrast to usual VC setup, here prover and verifier together must impose less overhead alternative executing directly on We instantiate this approach designing implementing physically realizable, area-efficient, high throughput ASICs (for verifier), fully synthesizable Verilog. The system, called Zebra, is based CMT Allspice interactive proof protocols, required new observations about CMT, careful design, attention architectural challenges. For class real computations, Zebra meets exceeds