Fast L1 flush mechanism
作者： Brian J. Campbell , James B. Keller , Ramesh Gunna , Tse-Yu Yeh
DOI:
关键词:
摘要: In one embodiment, a processor comprises data cache configured to store plurality of blocks and control unit coupled the cache. The is flush from responsive an indication that transition low power state in which or more clocks for are inhibited.
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