Method for testing real-time finite-sate machine in digital logic device
作者： Binbin Yuan , Lianchuan Ma , Xi Wang
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摘要: The invention discloses a method for testing real-time finite-sate machine in digital logic device, which comprises the following steps of: (S1) reducing cases to be tested, completing compilation of and generating test sequence; (S2) according full-automatic mode generate results; (S3) collecting results, sending results an upper computer. Wherein step specific (S1-1) starting from initial state S1 power on reset, traversing all I1 trigger input conditions state, checking whether transfer is correct or not; (S1-2) Ii next Si transferred normal mode, (S1-3) N states (S1-2); (S1-4) discretizing time constraint values triggerinput conditions. can solve problem explosive quantity efficiency greatly improved.
lens.org 参考文章(6)
Geoff Barrett, Method of generating a test suite ,(2002)
Sergey Olvovsky, Andrei Kirshin, Alan Hartman, Kenneth Nagin, Reducing the complexity of finite state machine test generation using combinatorial designs ,(2002)
Daniel H. Schaffer, Method and system for testing software using a finite state machine ,(1997)
Hiroaki Iwashita, 浩一郎 高山, Koichiro Takayama, 洋哲 岩下, Tsuneo Nakada, 恒夫 中田, Tsutomu Shu, Specification verification program, computer-readable recording medium with its program recorded thereon, specification verification device and specification verification method ,(2007)
Li Yunhua, Sun Yuntao, Testing method for limitting status machine of communication system ,(2005)
Xiaobo Chu, Xiaofeng Chen, Dengguo Feng, Hao Li, Min Zhang, Credible password module test case creation method and its test system ,(2008)