Compact circuit simulation model of silicon carbide static induction and junction field effect transistors
作者： A.S. Kashyap , P.L. Ramavarapu , S.M. Lal , T.R. McNutt , A.B. Lostefter
DOI: 10.1109/CIPE.2004.1428116
关键词:
摘要: The electrical characterization and model development for silicon carbide (SiC) vertical channel SIT JFET structures are presented in this work. A compact is developed based on the device geometry SiC material properties. validated against measured data at 25/spl deg/C 100/spl a prototype 0.03 cm/sup 2/ provided by Northrop Grumman. Validation also done power present combined MOSFET-SiC cascode structure from SiCED. model's on-state transient characteristics over temperature range. of shows excellent agreement with data. physics-based approach implemented crucial to describing behavior wide range application conditions ranges.
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