PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability
作者： Marc L. Harrison
DOI:
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摘要: A PLA (e.g., 100) operates with two-level clock control timing, that is, a pair of master and slave registers 12 13) connected to the wordlines W 1 , 2 . n ) between PLA's AND OR planes 11 14). The register's output plane is controlled by combinational logic device 21), such as an gate which WAIT signal applied. In this way, when W) available at beginning given cycle (including feedback) can respond before end cycle--that capable same-cycle decision making.
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