High-speed VLSI architectures for the AES algorithm
作者： Xinmiao Zhang , K.K. Parhi
DOI: 10.1109/TVLSI.2004.832943
关键词:
摘要: … Dr. Parhi is the recipient of numerous awards including the 2004 FE Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field …
acm.org
computer.org
idc-online.com 
sci-hub.se 参考文章(14)
Kris Gaj, Pawel Chodowiec, Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. AES Candidate Conference. pp. 40- 54 ,(2000)
Francois-Xavier Standaert, Gael Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat, Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs cryptographic hardware and embedded systems. ,vol. 2779, pp. 334- 350 ,(2003) , 10.1007/978-3-540-45238-6_27
M.H. Jing, Y.H. Chen, Y.T. Chang, C.H. Hsu, The design of a fast inverse module in AES international conferences on info tech and info net. ,vol. 3, pp. 298- 303 ,(2001) , 10.1109/ICII.2001.983073
G. P. Saggese, A. Mazzeo, N. Mazzocca, A. G. M. Strollo, An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm field-programmable logic and applications. pp. 292- 302 ,(2003) , 10.1007/978-3-540-45234-8_29
W. McLoone, J.V. McCanny, Rijndael FPGA implementation utilizing look-up tables signal processing systems. pp. 349- 360 ,(2001) , 10.1109/SIPS.2001.957363
Kimmo U. Järvinen, Matti T. Tommiska, Jorma O. Skyttä, A fully pipelined memoryless 17.8 Gbps AES-128 encryptor field programmable gate arrays. pp. 207- 215 ,(2003) , 10.1145/611817.611848
A.J. Elbirt, W. Yip, B. Chetwynd, C. Paar, An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists IEEE Transactions on Very Large Scale Integration Systems. ,vol. 9, pp. 545- 557 ,(2001) , 10.1109/92.931230
Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh, A Compact Rijndael Hardware Architecture with S-Box Optimization international conference on the theory and application of cryptology and information security. ,vol. 2248, pp. 239- 254 ,(2001) , 10.1007/3-540-45682-1_15
Christof Paar, B. Chetwynd, Adam J. Elbirt, W. Yip, An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists. AES Candidate Conference. pp. 13- 27 ,(2000)
Atri Rudra, Pradeep K. Dubey, Charanjit S. Jutla, Vijay Kumar, Josyula R. Rao, Pankaj Rohatgi, Efficient Rijndael Encryption Implementation with Composite Field Arithmetic cryptographic hardware and embedded systems. pp. 171- 184 ,(2001) , 10.1007/3-540-44709-1_16