An improved low-cost 6.4 Gbps wafer-level tester
作者： A.M. Majid , D.C. Keezer
DOI: 10.1109/EPTC.2005.1614511
关键词:
摘要: This paper describes an economical approach to high-speed testing of high-density wafer-level packaged logic devices. The solution assumes that the devices be tested have built-in self-test features, thereby reducing complexity functional required. also reduces need for expensive automated test equipment (ATE). A stand alone miniature tester is developed and connected top a wafer probe card with multiple (up 6.4 Gbps) signals. Off shelf components are used in order keep costs low. However its performance some aspects exceeds traditional ATE. Measurements illustrate generating Gbps signals plusmn25ps timing accuracy. generated exhibit low jitter ~40ps rise times on 50-70ps
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