Delayed precise invalidation-a software cache coherence scheme

摘要: Software-based cache coherence scheme is very desirable in scalable multiprocessor as well massively parallel processor designs. We propose a software-based named delayed precise invalidation. The invalidation based on compiler time markings of references and hardware-based local explicit stale data selectively. With small amount additional hardware set management instructions, the provides more cacheability allows partial elements an array, overcoming some inefficiencies deficiencies previous schemes. A correctness proof qualitative performance evaluation proposed are also presented. Finally, simulated hit ratios given. Simulation results show that outperforms by 1O%.