Reduction of the Feedback Capacitance of HFETs by Changing Transistor Layout and Using Via Holes for Source Grounding
作者： Niklas Rorsman , Mikael Garcia , Christer Karlsson , Herbert Zirath
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摘要: The influence of HFET layout and via holes on the feedback capacitance passive non-gated as well active HFETs has been examined. We have found that by careful design using via-hole for source grounding it is possible to reduce capacitance, thus improving high frequency characteristics HFET. total was reduced 70 % a device with varying one parameter. Results InP-based without via-holes show decrease 40 an InAlAs/InGaAs/InP maximum stable gain at GHz Was increased 1.5 dB changing layout.
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