作者: Yoichiro Tanaka , Roy E. Scheuerlein
DOI:
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摘要: The present invention provides apparatus, methods, and systems for fabricating memory lines structures using double sidewall patterning four times half pitch relief patterning. includes forming features from a first template layer disposed above substrate, half-pitch spacers adjacent the features, smaller in second by as hardmask, quarter-pitch conductor hardmask. Numerous additional aspects are disclosed.