Semiconductor power device having a diamond shaped metal interconnect scheme
作者： Yingping Zheng , Gennadiy Nemtsev , Rajesh Nair , Hui Wang
DOI:
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摘要: A transistor (10) is formed as a matrix of cells (13) that have drain metal strips (50) for contacting drains (15) the and source (55) sources (35) cells. An interconnect layer (1030) overlying has first portions (201) contact one with second vias (79) (101) third fourth (78).
lens.org 参考文章(12)
Taylor R. Efland, David Cotton, Dale J. Skelton, Multiple transistor integrated circuit with thick copper interconnect ,(1996)
Helmuth R. Litfin, James C. Moyer, Martin J. Alter, Method of making a diamond shaped gate mesh for cellular MOS transistor array ,(1994)
Toshiaki Hasegawa, Hajime Nakayama, Semiconductor device having low dielectric layer and method of manufacturing thereof ,(2001)
Alfonso Maurelli, Nicola Zatelli, Massimo Ati, Method of forming low-resistivity connections in non-volatile memories ,(2001)
James S. Koford, Stanislav V. Aleshin, Alexander S. Podkolzin, Ranko Scepanovic, Alexander E. Andreev, Valeriy B. Kudryavtsev, Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry ,(1995)
Charles Nickel, Conductive routings in integrated circuits ,(2002)
Taylor R. Efland, Dave Cotton, Dale J. Skelton, Ldmos transistor with thick copper interconnect ,(1995)
Charles Nickel, Andrew J. Burstein, Transistor pattern for voltage regulator ,(2001)
Michael Keller, Wolfgang Jorger, Achim Stellberger, Sub-milliohm on-chip interconnection ,(2001)
Taylor R. Efland, Michael C. Smayling, Satwinder Malhi, Joseph A. Devore, Alec J. Morton, Ross E. Teggatz, Method for current ballasting and busing over active device area using a multi-level conductor process ,(1997)