作者: Xu He , Tao Huang , Wing-Kai Chow , Jian Kuang , Ka-Chun Lam
关键词:
摘要: Due to a significant mismatch between the objectives of wirelength and routing congestion, routability issue is becoming more important in VLSI design. In this paper, we present high quality placer Ripple 2.0 solve routability-driven placement problem. We will study how make use path information cell spreading relieve congestion with tangled logic detail. Several techniques are proposed, including (1) lookahead analysis pin density consideration, (2) path-based inflation (3) robust optimization on congested cluster. With official evaluation protocol, outperforms top contestants ICCAD 2012 Contest benchmark suite.